Bộ DEMUX8_1

-------------------------------------------------------------------------------
--
-- Title       : DEMUX8_1
-- Design      : baithuchanh1
-- Author      : phamthanh1992@hotmail.com
-- Company     : homes
--
-------------------------------------------------------------------------------
--
-- File        : DEMUX8_1.vhd
-- Generated   : Thu May  2 21:04:46 2013
-- From        : interface description file
-- By          : Itf2Vhdl ver. 1.22
--
-------------------------------------------------------------------------------
--
-- Description : 
--
-------------------------------------------------------------------------------

--{{ Section below this comment is automatically maintained
--   and may be overwritten
--{entity {DEMUX8_1} architecture {DEMUX8_1}}

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity DEMUX1_8 is
port(
x : in STD_LOGIC;
sel : in STD_LOGIC_VECTOR(2 downto 0);
y : out STD_LOGIC_VECTOR(7 downto 0)
    );
end DEMUX1_8;

--}} End of automatically maintained section

architecture DEMUX1_8 of DEMUX1_8 is
begin

with sel select
y<="ZZZZZZZ"&x when "000",
"ZZZZZZ"&x&'Z' when "001",
"ZZZZZ"&x&"ZZ" when "010",
"ZZZZ"&x&"ZZZ" when "011",
"ZZZ"&x&"ZZZZ" when "100",
"ZZ"&x&"ZZZZZ" when "101",
'Z'&x&"ZZZZZZ" when "110",
x&"ZZZZZZZ" when "111",
unaffected when others;

end DEMUX1_8;