Đếm BCD hiển thị led 7 thanh

Cách 1:
library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity Dem_BCD is
port(
clk : in STD_LOGIC;
rst : in STD_LOGIC;
sel : in STD_LOGIC;
Q : out STD_LOGIC_VECTOR(6 downto 0)
    );
end Dem_BCD;

--}} End of automatically maintained section

architecture Dem_BCD of Dem_BCD is
begin
process(clk,rst,sel)
variable x:integer range 0 to 9;
begin
if rst='1' then
x:=0;
else
if clk'event and clk='1'then 
if sel='1' then
if x=9 then
x:=0;
else
x:=x+1;
end if;
else
if x=0 then
x:=9;
else
x:=x-1;
end if;
end if;
end if;
end if;
case x is
when 0 =>Q<="1111110";
when 1 =>Q<="0110000";
when 2 =>Q<="1100101";
when 3 =>Q<="1111001";
when 4 =>Q<="0110011";
when 5 =>Q<="1011011";
when 6 =>Q<="1011111";
when 7 =>Q<="1110000";
when 8 =>Q<="1111111";
when 9 =>Q<="1111011";
end case;
end process;

-- enter your statements here --

end Dem_BCD;

Cách 2 :

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity DEM_BCD_2 is
port(
clk : in STD_LOGIC;
rst : in STD_LOGIC;
sel : in STD_LOGIC;
Q   : out STD_LOGIC_VECTOR(6 downto 0)
    );
end DEM_BCD_2;

--}} End of automatically maintained section

architecture DEM_BCD_2 of DEM_BCD_2 is
type state is (s0,s1,s2,s3,s4,s5,s6,s7,s8,s9);
signal s:state;
begin
next_state:process(rst,clk,sel)
begin
if rst ='1' then
s<=s0;
else
if clk'event and clk='1'then
if sel='1'then
case s is
when s0=>s<=s1;
when s1=>s<=s2;
when s2=>s<=s3;
when s3=>s<=s4;
when s4=>s<=s5;
when s5=>s<=s6;
when s6=>s<=s7;
when s7=>s<=s8;
when s8=>s<=s9;
when s9=>s<=s0;
end case;
else
case s is
when s0=>s<=s9;
when s1=>s<=s0;
when s2=>s<=s1;
when s3=>s<=s2;
when s4=>s<=s3;
when s5=>s<=s4;
when s6=>s<=s5;
when s7=>s<=s6;
when s8=>s<=s7;
when s9=>s<=s8;
end case;
end if;
end if;  
end if;
end process;

output_state:process(s)
begin
case s is
when s0 =>Q<="1111110";
when s1 =>Q<="0110000";
when s2 =>Q<="1100101";
when s3 =>Q<="1111001";
when s4 =>Q<="0110011";
when s5 =>Q<="1011011";
when s6 =>Q<="1011111";
when s7 =>Q<="1110000";
when s8 =>Q<="1111111";
when s9 =>Q<="1111011";
end case;
end process;
-- enter your statements here --


end DEM_BCD_2;

Mahoa

-------------------------------------------------------------------------------
--
-- Title       : Mahoa
-- Design      : baithuchanh1
-- Author      : phamthanh1992@hotmail.com
-- Company     : homes
--
-------------------------------------------------------------------------------
--
-- File        : Mahoa.vhd
-- Generated   : Thu May  2 21:36:17 2013
-- From        : interface description file
-- By          : Itf2Vhdl ver. 1.22
--
-------------------------------------------------------------------------------
--
-- Description :
--
-------------------------------------------------------------------------------

--{{ Section below this comment is automatically maintained
--   and may be overwritten
--{entity {Mahoa} architecture {Mahoa}}

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity Mahoa is
port(
A : in STD_LOGIC_VECTOR(3 downto 0);
G : out STD_LOGIC_VECTOR(3 downto 0)
    );
end Mahoa;

--}} End of automatically maintained section

architecture Mahoa of Mahoa is
begin
with A select
G<= "0000" when "0000",
"0001" when "0001",
"0010" when "0011",
"0011" when "0010",
"0100" when "0110",
"0101" when "0111",
"0110" when "0101",
"0111" when "0100",
"1000" when "1100",
"1001" when "1101",
"1010" when "1111",
"1011" when "1110",
"1100" when "1010",
"1101" when "1011",
"1110" when "1001",
"1111" when "1000",
"XXXX" when others;

-- enter your statements here --

end Mahoa;

Bộ DEMUX8_1

-------------------------------------------------------------------------------
--
-- Title       : DEMUX8_1
-- Design      : baithuchanh1
-- Author      : phamthanh1992@hotmail.com
-- Company     : homes
--
-------------------------------------------------------------------------------
--
-- File        : DEMUX8_1.vhd
-- Generated   : Thu May  2 21:04:46 2013
-- From        : interface description file
-- By          : Itf2Vhdl ver. 1.22
--
-------------------------------------------------------------------------------
--
-- Description : 
--
-------------------------------------------------------------------------------

--{{ Section below this comment is automatically maintained
--   and may be overwritten
--{entity {DEMUX8_1} architecture {DEMUX8_1}}

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity DEMUX1_8 is
port(
x : in STD_LOGIC;
sel : in STD_LOGIC_VECTOR(2 downto 0);
y : out STD_LOGIC_VECTOR(7 downto 0)
    );
end DEMUX1_8;

--}} End of automatically maintained section

architecture DEMUX1_8 of DEMUX1_8 is
begin

with sel select
y<="ZZZZZZZ"&x when "000",
"ZZZZZZ"&x&'Z' when "001",
"ZZZZZ"&x&"ZZ" when "010",
"ZZZZ"&x&"ZZZ" when "011",
"ZZZ"&x&"ZZZZ" when "100",
"ZZ"&x&"ZZZZZ" when "101",
'Z'&x&"ZZZZZZ" when "110",
x&"ZZZZZZZ" when "111",
unaffected when others;

end DEMUX1_8;