Mahoa

-------------------------------------------------------------------------------
--
-- Title       : Mahoa
-- Design      : baithuchanh1
-- Author      : phamthanh1992@hotmail.com
-- Company     : homes
--
-------------------------------------------------------------------------------
--
-- File        : Mahoa.vhd
-- Generated   : Thu May  2 21:36:17 2013
-- From        : interface description file
-- By          : Itf2Vhdl ver. 1.22
--
-------------------------------------------------------------------------------
--
-- Description :
--
-------------------------------------------------------------------------------

--{{ Section below this comment is automatically maintained
--   and may be overwritten
--{entity {Mahoa} architecture {Mahoa}}

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity Mahoa is
port(
A : in STD_LOGIC_VECTOR(3 downto 0);
G : out STD_LOGIC_VECTOR(3 downto 0)
    );
end Mahoa;

--}} End of automatically maintained section

architecture Mahoa of Mahoa is
begin
with A select
G<= "0000" when "0000",
"0001" when "0001",
"0010" when "0011",
"0011" when "0010",
"0100" when "0110",
"0101" when "0111",
"0110" when "0101",
"0111" when "0100",
"1000" when "1100",
"1001" when "1101",
"1010" when "1111",
"1011" when "1110",
"1100" when "1010",
"1101" when "1011",
"1110" when "1001",
"1111" when "1000",
"XXXX" when others;

-- enter your statements here --

end Mahoa;

Bộ DEMUX8_1

-------------------------------------------------------------------------------
--
-- Title       : DEMUX8_1
-- Design      : baithuchanh1
-- Author      : phamthanh1992@hotmail.com
-- Company     : homes
--
-------------------------------------------------------------------------------
--
-- File        : DEMUX8_1.vhd
-- Generated   : Thu May  2 21:04:46 2013
-- From        : interface description file
-- By          : Itf2Vhdl ver. 1.22
--
-------------------------------------------------------------------------------
--
-- Description : 
--
-------------------------------------------------------------------------------

--{{ Section below this comment is automatically maintained
--   and may be overwritten
--{entity {DEMUX8_1} architecture {DEMUX8_1}}

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity DEMUX1_8 is
port(
x : in STD_LOGIC;
sel : in STD_LOGIC_VECTOR(2 downto 0);
y : out STD_LOGIC_VECTOR(7 downto 0)
    );
end DEMUX1_8;

--}} End of automatically maintained section

architecture DEMUX1_8 of DEMUX1_8 is
begin

with sel select
y<="ZZZZZZZ"&x when "000",
"ZZZZZZ"&x&'Z' when "001",
"ZZZZZ"&x&"ZZ" when "010",
"ZZZZ"&x&"ZZZ" when "011",
"ZZZ"&x&"ZZZZ" when "100",
"ZZ"&x&"ZZZZZ" when "101",
'Z'&x&"ZZZZZZ" when "110",
x&"ZZZZZZZ" when "111",
unaffected when others;

end DEMUX1_8;